Microchip accelerates development of 800G active electrical cables - The EE

Microchip accelerates development of 800G active electrical cables

Colorful Plastic Polymer Granules for cable Image by fabrikasimf on Freepik

Microchip Technology has announced an accelerated development path for quad small form factor pluggable double density (QSFP-DD) and octal small form factor pluggable (OSFP) active electrical cables (AECs) using its META-DX2C 800G retimer. The announcement comes as the rise of generative AI and AI/ML technologies fuels the demand for more high-speed connections and the push toward 800G connectivity in backend data centre networks and applications. However, cable vendors face numerous design and development hurdles that need to be overcome.

The retimer is supported by a comprehensive formula for 800G AEC product development including a hardware reference design and complete common management interface specification (CMIS) software package to minimise development resources needed for cable manufacturers.

“The newest and most compact member of our META-DX2 Ethernet PHY family leverages Microchip’s unique breadth of microcontrollers and other key components to provide a complete reference design that accelerates AEC product development, reduces resource investments, and simplifies supply-chain management,” said Maher Fahmi, a vice president for Microchip’s communications business unit. “The META-DX2C retimer enables AEC connections for the high-density networks that are needed for generative AI applications.”

The META-DX2C retimer uses high-performance, long-reach 112G SerDes that can support up to 40 dB reach, enabling the design of thinner and longer AECs that are important for dense hyperscaler infrastructure build outs. Additionally, Microchip is offering a validated paddle card hardware reference design and a software package that implements the CMIS software in a Microchip 32-bit PIC32 microcontroller. Microchip’s META-DX2C compact retimer can also solve similar connectivity challenges in high-capacity data centre switches and routers where high density and data rates create signal integrity problems.

This retimer supports a bi-directional 800G maximum capacity in retiming applications and up to 400G capacity in the gearbox and 2:1 multiplexing applications. It also features up to 16 SerDes and a flexible crosspoint. The SerDes are all long reach (LR) capable of supporting up to 40dB of loss as well as link training and auto-negotiation.

“Generative AI is impacting how data centre infrastructure is being built and the amount of network connectivity that is required, in a big way,” said Alan Weckel, a co-founder and analyst with market research firm 650 Group. “To address this challenge, hyperscalers need solutions that are very high bandwidth as well as low power and low cost. We are seeing a transition to active electrical cables as the optimal solution for this challenge. Microchip’s META-DX2C 800G AEC retimer is aligned with this trend and is the type of solution needed to enable growth in this area.”

Development Package

Microchip ’s META-DX2C 800G AEC formula is supported by a paddle card reference design that includes the META-DX2C retimer, PIC32 microcontroller, oscillators, buck regulator, and linear voltage regulator, all from Microchip. Having these elements available from a single supplier can simplify a customer’s supply chain management. The included software development kit supports the CMIS 5.2 specification.


The META-DX2C retimer, part #PM6254, with the hardware reference design, firmware solution, and SDK, is available now. For additional information visit the META-DX family webpage or contact a Microchip sales representative.

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